- 您现在的位置：买卖IC网 > Sheet目录1203 > COREPCIF-RM (Microsemi SoC)IP MODULE COREPCIF
Backend Master Dataflow Signals
The additional signals in Table 5-5 are used only for Master data transfers between the core and the user’s backend logic.
These signals only function when the MASTER parameter is set. All these inputs and outputs are synchronous to the
PCI clock.
Table 5-5 · Master Mode Signals
Name
Type
Width
Description
Indicates (active high) that the current transaction is a Master transaction initiated by the
DMA engine. MAST_ACTIVE becomes active one clock cycle before DP_START and
MAST_ACTIVE
Output
1
goes inactive one clock cycle before DP_DONE. This output can be delayed externally by
a clock cycle so it aligns with DP_START, DP_DONE, and the other backend control
signals if required.
Indicates (active high) that the core is processing a DMA request. This signal becomes
MAST_BUSY
Output
1
active when the DMA request is set in the DMA control register and stays active until the
DMA completes.
Indicates which BAR the DMA engine wishes to access. This output can be used with
DMA_BAR
Output
3
multiple FIFOs on the backend to multiplex their EMPTY/FULL signals to the
RD_BUSY_MASTER and WR_BUSY_MASTER inputs.
WR_BUSY_MASTER
RD_BUSY_MASTER
Input
Input
1
1
When HIGH, a DMA write to the backend cycle will not be started.
When HIGH, a DMA read from the backend cycle will not be started.
When HIGH, an active DMA cycle will be stopped. Once asserted, this signal should be
held asserted until DP_DONE is asserted. It may continue to be held active after
DP_DONE has been asserted. If active when a DMA cycle starts, the core will transfer
one word on the PCI bus before terminating the PCI transfer.
After STOP_MASTER is asserted, it is possible that one or more data transfers to or
STOP_MASTER
Input
1
from the backend may occur. For backend write cycles, one more data transfer will always
occur. For backend read cycles, additional data transfers will happen if RD_STB_OUT
was active and RD_STB_IN was inactive the clock cycle before STOP_MASTER was
asserted.
Typically, a FIFO empty output will be directly connected to both the RD_STB_IN and
STOP_MASTER inputs.
If HIGH when CorePCIF starts a DMA cycle on the backend, the core will assert
DP_START and delay asserting FRAME on the PCI bus until STALL_MASTER is
deasserted (LOW), which signifies that the backend's data is now ready. This can be used
STALL_MASTER
Input
1
to support backends that take many clock cycles to become ready. STALL_MASTER
must be asserted on the clock cycle after MAST_ACTIVE becomes active. This is the
same cycle in which DP_START occurs.
The operation of the STALL_MASTER input is described in detail in
48
v4.0
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
COREU1LL-AR
IP MODULE COREU1LL
COREU1PHY-AR
IP MODULE COREU1PHY
CORR-8BIT-XM-UT2
SITE LICENSE IP CORRELATOR XP
CP2-GSA-L
CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1
CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4
CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F
COMPACT PCI - MISC
CP2105EK
KIT EVAL FOR CP2105
相关代理商/技术参数
COREPCIF-RMFL
功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR
功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B
制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E
制造商:Philips Lumileds 功能描述: